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? semiconductor components industries, llc, 2016 march, 2016 ? rev. 7 1 publication order number: ncp1631/d ncp1631 interleaved, 2-phase power factor controller the ncp1631 integrates a dual mosfet driver for interleaved pfc applications. interleaving consists of paralleling two small stages in lieu of a bigger one, more difficult to design. this approach has several merits like the ease of implementation, the use of smaller components or a better distribution of the heating. also, interleaving extends the power range of critical conduction mode that is an efficient and cost?effective technique (no need for low t rr diodes). in addition, the ncp1631 drivers are 180 phase shift for a significantly reduced current ripple. housed in a soic16 package, the circuit incorporates all the features necessary for building robust and compact interleaved pfc stages, with a minimum of external components. general features ? near?unity power factor ? substantial 180 phase shift in all conditions including transient phases ? frequency clamped critical conduction mode ( fccrm ) i.e., fixed frequency, discontinuous conduction mode operation with critical conduction achievable in most stressful conditions ? fccrm operation optimizes the pfc stage efficiency over the load range ? out?of?phase control for low emi and a reduced rms current in the bulk capacitor ? frequency fold?back at low power to further improve the light load efficiency ? accurate zero current detection by auxiliary winding for valley turn on ? fast line / load transient compensation ? high drive capability: ?500 ma / +800 ma ? signal to indicate that the pfc is ready for operation (?pfcok? pin) ? v cc range: from 10 v to 20 v safety features ? output over and under voltage protection ? brown?out detection with a 50?ms delay to help meet hold?up time specifications ? soft?start for smooth start?up operation ? programmable adjustment of the maximum power ? over current limitation ? detection of inrush currents typical applications ? computer power supplies ? lcd / plasma flat panels ? all off line appliances requiring power factor correction *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soic?16 d suffix case 751b device package shipping ? ordering information NCP1631DR2G soic?16 (pb?free) 2500 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. pin assignment (top view) zcd1 ref5v/pfcok drv1 gnd vcc drv2 latch cs zcd2 fb rt osc vcontrol ffold bo ovp / uvp 1 marking diagram ncp1631g awlyww a = assembly location wl = wafer lot y = year ww = work week g = pb?free package www. onsemi.com
ncp1631 www. onsemi.com 2 emi filter ac lin e vin load vout cin 1 2 3 413 16 14 15 5 6 7 12 10 11 vcc pfcok vout figure 1. typical application schematic l 2 i coil2 d 2 c bulk m 2 m 1 d 1 i coil1 l 1 v aux2 r zcd1 9 r cs r ocp ovp in i in 8 r zcd2 v aux2 c comp1 c bo2 r comp1 c comp2 c osc r ff r t r bo2 r bo1 r ovp1 r ovp2 ovp in r out1 r out2 table 1. maximum ratings symbol rating pin value unit v cc(max) maximum power supply v oltage continuous 12 ?0.3, +20 v v max maximum input voltage on low power pins 1, 2, 3, 4, 6, 7, 8, 9, 10, 15, and 16 ?0.3, +9.0 v v control(max) v control pin maximum input voltage 5 ?0.3, v control(clamp) (note 1) v p d r j?a power dissipation and thermal characteristics maximum power dissipation @ t a = 70 c thermal resistance junction?to?air 550 145 mw c/w t j operating junction temperature range ?55 to +150 c t j(max) maximum junction t emperature 150 c t s(max) storage temperature range ?65 to +150 c t l(max) lead temperature (soldering, 10s) 300 c esd capability, hbm model (note 2) 3 kv esd capability, machine model (note 2) 250 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. ?v control(clamp) ? is the pin5 clamp voltage. 2. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22?a114e machine model method 200 v per jedec standard jesd22?a115?a 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78.
ncp1631 www. onsemi.com 3 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v; for typical values t j = 25 c, for min/max values t j = ?55 c to +125 c, unless otherwise specified) (note 6) characteristics test conditions symbol min typ max unit startup and supply circuits supply v oltage startup threshold minimum operating v oltage hysteresis v cc(on) ? v cc(off) internal logic reset v cc increasing v cc decreasing v cc decreasing v cc(on) v cc(off) v cc(hyst) v cc(reset) 11 9.5 1.5 4.0 11.85 10 1.85 5.75 12.7 10.5 ? 7.5 v startup current v cc = 9.4 v i cc(start) ? 35 100 a supply current device enabled/no output load on pin6 current that discharges v cc in latch mode current that discharges v cc in off mode f sw = 130 khz (note 4) v cc = 15 v, v pin10 = 5 v v cc = 15 v, pin 7 grounded i cc1 i cc(latch) i cc(off) ? ? ? 5.0 0.4 0.4 7.0 0.8 0.8 ma oscillator and frequency foldback clamping charging current pin 6 open t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) i osc(clamp) 31.5 30 35 35 38.5 38.5 a charge current with no frequency foldback pin 6 grounded t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) i osc(ch1) 126 120 140 140 154 154 a charge current @ i pin6 = 50 a i pin6 = 50 a i osc(ch2) 76.5 85 93.5 a maximum discharge current with no frequency foldback pin 6 grounded t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) i osc(disch1) 94.5 90 105 105 115.5 115.5 a discharge current @ i pin6 = 50 a i pin6 = 50 a i osc(disch2) 45 50 55 a voltage on pin 6 i pin6 = 50 a, v pin5 = 2.5 v v ff 0.9 1.0 1.3 v oscillator upper threshold v osc(high) ? 5 ? v oscillator lower threshold v osc(low) 3.6 4.0 4.4 v oscillator swing (note 5) v osc(swing) 0.93 0.98 1.03 v current sense current sense voltage of fset i pin9 = 100 a i pin9 = 10 a v cs(th100) v cs(th10) ?20 ?10 0 0 20 10 mv current sense protection threshold t j = 25 c t j = ?40 c to 125 c t j = ?55 c to +125 c (note 6) i ilim1 202 194 173 210 210 210 226 226 226 a threshold for in?rush current detection (note 5) t j = ?40 c to +125 c t j = ?55 c to +125 c i in?rush 11 10.4 14 14 17 17 a gate drive drive resistance drv1 sink drv1 source drv2 sink drv2 source i pin14 = 100 ma i pin14 = ?100 ma i pin11 = 100 ma i pin11 = ?100 ma r snk1 r src1 r snk2 r src2 ? ? ? ? 7 15 7 15 15 25 15 25 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design and characterization. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1631 www. onsemi.com 4 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v; for typical values t j = 25 c, for min/max values t j = ?55 c to +125 c, unless otherwise specified) (note 6) characteristics unit max typ min symbol test conditions gate drive drive current capability (note 5) drv1 sink drv1 source drv2 sink drv2 source v drv1 = 10 v v drv1 = 0 v v drv2 = 10 v v drv2 = 0 v i snk1 i src1 i snk1 i src1 ? ? ? ? 800 500 800 500 ? ? ? ? ma rise time drv1 drv2 c drv1 = 1 nf, v drv1 = 1 to 10 v c drv2 = 1 nf, v drv2 = 1 to 10 v t r1 t r2 ? ? 40 40 ? ? ns fall time drv1 drv2 c drv1 = 1 nf, v drv1 = 10 to 1 v c drv2 = 1 nf, v drv2 = 10 to 1 v t f1 t f2 ? ? 20 20 ? ? ns regulation block feedback voltage reference v ref 2.44 2.500 2.56 v error amplifier source current capability @ v pin2 = 2.4 v i ea(src) ?20 a error amplifier sink current capability @ v pin2 = 2.6 v i ea(snk) +20 error amplifier gain g ea 110 200 290 s pin 5 source current when (v out(low) detect) is activated t j = ?40 c to 125 c t j = ?55 c to +125 c (note 6) i control(boost) 184 178 230 230 276 276 a a pin2 bias current v pin2 = 2.5 v i fb(bias) ?500 500 na pin 5 v oltage: @ v pin2 = 2.4 v @ v pin2 = 2.6 v v control(clamp) v control(min) v control(range) 3.0 0 2.7 3.6 0.6 3 4.2 1.2 3.3 v internal v regul voltage (measured on pin 6): @ v pin2 = 2.6 v, i pin6 = 90 a @ v pin2 = 2.4 v, i pin6 = 90 a v regul(min) v regul(clamp) ? ? ? 1.66 0.1 ? v ratio (v out(low) detect threshold / v ref ) (note 5) fb falling v out(low) /v ref 95.0 95.5 96.0 % ratio (v out(low) detect hysteresis / v ref ) (note 5) fb rising h out(low) /v ref ? ? 0.5 % skip mode duty cycle v pin2 = 3 v d min ? ? 0 % ramp control (valid for the two phases) maximum drv1 and drv2 on?time (fb pin grounded) t j = ?25 c to +125 c v pin7 = 1.1 v, i pin3 = 50 a v pin7 = 1.1 v, i pin3 = 200 a (note 5) v pin7 = 2.2 v, i pin3 = 100 a (note 5) v pin7 = 2.2 v, i pin3 = 400 a (note 5) t on1 t on2 t on3 t on4 14.5 1.10 4.00 0.35 19.5 1.35 5.00 0.41 22.5 1.60 6.00 0.48 s maximum drv1 and drv2 on?time (fb pin grounded) t j = ?40 c to +125 c v pin7 = 1.1 v, i pin3 = 50 a v pin7 = 1.1 v, i pin3 = 200 a (note 5) v pin7 = 2.2 v, i pin3 = 100 a (note 5) v pin7 = 2.2 v, i pin3 = 400 a (note 5) t on1 t on2 t on3 t on4 14.0 1.05 3.84 0.33 19.5 1.35 5.00 0.41 22.5 1.60 6.00 0.48 s maximum drv1 and drv2 on?time (fb pin grounded) t j = ?55 c to +125 c v pin7 = 1.1 v, i pin3 = 50 a (note 6) v pin7 = 1.1 v, i pin3 = 200 a (note 5) v pin7 = 2.2 v, i pin3 = 100 a (note 5) v pin7 = 2.2 v, i pin3 = 400 a (note 5) t on1 t on2 t on3 t on4 13.0 1.00 3.70 0.32 19.5 1.35 5.00 0.41 22.5 1.60 6.00 0.48 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design and characterization. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1631 www. onsemi.com 5 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v; for typical values t j = 25 c, for min/max values t j = ?55 c to +125 c, unless otherwise specified) (note 6) characteristics unit max typ min symbol test conditions ramp control (valid for the two phases) pin 3 voltage v bo = v pin7 = 1.1 v, i pin3 = 50 a v bo = v pin7 = 1.1 v, i pin3 = 200 a v bo = v pin7 = 2.2 v, i pin3 = 50 a v bo = v pin7 = 2.2 v, i pin3 = 200 a v rt1 v rt2 v rt3 v rt4 1.071 1.071 2.169 2.169 1.096 1.096 2.196 2.196 1.121 1.121 2.223 2.223 v maximum v ton voltage not tested v ton(max) 5 v pin 3 current capability i rt(max) 1 ? ? ma pin 3 sourced current below which the controller is off i rt(off) 7 a pin 3 current range not tested i rt(range) 20 1000 a zero voltage detection circuit (valid for zcd1 and zcd2) zcd threshold voltage v zcd increasing v zcd falling v zcd(th),h v zcd(th),l 0.40 0.20 0.50 0.25 0.60 0.30 v zcd hysteresis v zcd decreasing v zcd(hys) 0.25 v input clamp v oltage high state low state i pin1 = 5.0 ma i pin1 = ?5.0 ma v zcd(high) v zcd(low) 9.0 ?1.1 11 ?0.65 13 ?0.1 v internal input capacitance (note 5) c zcd ? 10 ? pf zcd watchdog delay t zcd 80 200 320 s brown?out detection brown?out comparator threshold v bo(th) 0.97 1.00 1.03 v brown?out current source t j = ?40 c to 125 c t j = ?55 c to +125 c (note 6) i bo 6 5.7 7 7 8 8 a brown?out blanking time (note 5) t j = ?40 c to 125 c t j = ?55 c to +125 c t bo(blank) 38 38 50 50 62 63.5 ms brown?out monitoring window (note 5) t bo(window) 38 50 62 ms pin 7 clamped voltage if v bo < v bo(th) during t bo(blank) i pin7 = ?100 a v bo(clamp) ? 965 ? mv current capability of the bo clamp i bo(clamp) 100 ? ? a hysteresis v bo(th) ? v bo(clamp) i pin7 = ? 100 a v bo(hys) 10 35 60 mv current capability of the bo pin clamp pnp transistor i bo(pnp) 100 ? ? a pin bo voltage when clamped by the pnp i pin7 = ? 100 a v bo(pnp) 0.35 0.70 0.90 v over and under voltage protections over?voltage protection threshold v ovp 2.425 2.500 2.575 v ratio (v ovp / v ref ) (note 5) v ovp /v ref 99.2 99.7 100.2 % ratio uvp threshold over v ref v uvp /v ref 8 12 16 % pin 8 bias current v pin8 = 2.5 v v pin8 = 0.3 v i ovp(bias) ?500 ? 500 na latch input pin latch threshold for shutdown v latch 2.375 2.500 2.625 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design and characterization. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1631 www. onsemi.com 6 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v; for typical values t j = 25 c, for min/max values t j = ?55 c to +125 c, unless otherwise specified) (note 6) characteristics unit max typ min symbol test conditions latch input pin latch bias current v pin10 = 2.3 v i latch(bias) ?500 ? 500 na pfcok / ref5v pin 15 voltage low state v pin7 = 0 v, i pin15 = 250 a v ref5v(low) ? 60 120 mv pin 15 voltage high state v pin7 = 0 v, i pin15 = 5 ma v ref5v(high) 4.7 4.85 5.3 v current capability i ref5v 5 10 ? ma thermal shutdown thermal shutdown threshold t shdn 130 140 150 c thermal shutdown hysteresis t shdn(hys) ? 50 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design and characterization. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1631 www. onsemi.com 7 table 3. detailed pin description pin number name function 1 zcd2 this is the zero current detection pin for phase 2 of the interleaved pfc stage. apply the voltage from an auxiliary winding to detect the core reset of the inductor and the valley of the mosfet drain source voltage 2 fb this pin receives a portion of the pre?converter output voltage. this information is used for the reg- ulation and the ?output low? detection (v out l) that drastically speed?up the loop response when the output voltage drops below 95.5% of the wished level. 3 r t the resistor placed between pin 3 and ground adjusts the maximum on?time of our system for both phases, and hence the maximum power that can be delivered by the pfc stage. 4 osc connect a capacitor to set the clamp frequency of the pfc stage. if wished, this frequency can be reduced in light load as a function of the resistor placed between pin 6 and ground (frequency fold?back). if the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. hence, the pfc stage can operate in critical conduction mode in the most stressful conditions. 5 v control the error amplifier output is available on this pin. the capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve high power factor ratios. pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft?start). 6 freq. foldback apply a resistor between pin 6 and ground to adjust the oscillator charge current. clamped not to exceed 100 a, this charge current is made proportional to the power level for a reduced switching frequency at light load and an optimum efficiency over the load range. 7 bo (brown?out protection) apply an averaged portion of the input voltage to detect brown?out conditions when v pin2 drops below 1 v. a 50?ms internal delay blanks short mains interruptions to help meet hold?up time re- quirements. when it detects a brown?out condition, the circuit stops pulsing and grounds the ?pfcok? pin to disable the downstream converter. also an internal 7? a current source is activated to offer a programmable hysteresis. the pin2 voltage is internally re?used for feed?forward. grounding pin 7 disables the part (after the 50?ms blanking time has elapsed). 8 ovp / uvp the circuit turns off when v pin9 goes below 480 mv (uvp) and disables the drive as long as the pin voltage exceeds 2.5 v (ovp). 9 cs this pin monitors a negative voltage proportional to the coil current. this signal is sensed to limit the maximum coil current and protect the pfc stage in presence of in?rush currents. 10 latch apply a voltage higher than 2.5 v to latch?off the circuit. the device is reset by unplugging the pfc stage (practically when the circuit detects a brown?out detection) or by forcing the circuit v cc below v cc rst (4 v typically). operation can then resume when the line is applied back. 11 drv2 this is the gate drive pin for phase 2 of the interleaved pfc stage. the high current capability of the totem pole gate drive (+0.5/?0.8 a) makes it suitable to effectively drive high gate charge power mosfets. 12 v cc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 12 v and turns off when v cc goes below 10 v (typical values). after start?up, the operating range is 9.5 v up to 20 v. 13 gnd connect this pin to the pre?converter ground. 14 drv1 this is the gate drive pin for phase 1 of the interleaved pfc stage. the high current capability of the totem pole gate drive (+0.5/?0.8 a) makes it suitable to effectively drive high gate charge power mosfets. 15 ref5v / pfcok the pin15 voltage is high (5 v) when the pfc stage is in a normal, steady state situation and low otherwise. this signal serves to ?inform? the downstream converter that the pfc stage is ready and that hence, it can start operation. 16 zcd1 this is the zero current detection pin for phase 1 of the interleaved pfc stage. apply the voltage from an auxiliary winding to detect the core reset of the inductor and the valley of the mosfet drain source voltage.
ncp1631 www. onsemi.com 8 drv1 vd d regul vcc ou tpu t buffer 1 internal ts d of f uvlo fb vcontrol rt vton processing circuitry vton zcd2 gnd dt shdn of f osc iref + ? vovp = vref ovp off shdn + ? error amplifier vref + ? 0.955* vr ef vout low detect ffold vcc 3v 5r ref5v bo ovp off ovlflag1 all the rs latches are reset dom inant stup zcd1 latch + ? vr ef + ? 12% vr ef uvp bo_nok vcc_ok pfcok 230 a vd d vref pfcok ovlflag1 lstup 4r dt drv1 fault management oc p in?rush + ? ics cs sk i p ( 0.6 v cl amp vo ltag e i s acti vated) uvp in?rush vcc < vcc(r eset) vcc(on) vcc(off) ovp drv2 ou tpu t buffer 2 vcc bo_nok brown?out 50?ms delay drv2 l shdn off skip oc p stop vpwm2 stop vpwm1 stop clk1 clk2 clk1 clk2 vpwm1 vpwm2 drv1 drv2 drv1 drv2 pfcok irt_low irt_low in?rush in?rush in?rush bo_nok vcc_ok pfcok figure 2. functional block diagram pfcok/ ref5v r s q v zcd1 v dmg1 v zcd2 v dmg2 v bo zero current detection for phase 1 zero current detection for phase 2 v bocomp detection with v bo q zcd1 q zcd2 i cs > 210 a i cs > 14 a current sense block (building of i cs proportional to i coil ) s r q i ff v zcd1 v zcd2 i ch oscillator block with interleaving and frequency foldback s r q l pwm1 s q r l pwm2 thermal shutdown 20 a i ff v regul i rt < 7 a v bocomp generation of the oscillator charge current i ff as a function of v regul (frequency fold?back) generation of the charge current for the internal timing capacitors (max on?time setting for the two phases) on?time control for the two phases
ncp1631 www. onsemi.com 9 detailed operating description the ncp1631 integrates a dual mosfet driver for interleaved, 2?phase pfc applications. it drives the two branches in so?called f requency c lamped cr itical conductio n m ode ( fccrm ) where each phase operates in cr itical conduction m ode (crm) in the most stressful conditions and in d iscontinuous c onduction m ode (dcm) otherwise, acting as a crm controller with a frequency clamp (given by the oscillator). according to the conditions, the pfc stage actually jumps from dcm to crm (and vice versa) with no discontinuity in operation and without degradation of the current shape. furthermore, the circuit incorporates protection features for a rugged operation together with some special circuitry to lower the power consumed by the pfc stage in no?load conditions. more generally, the ncp1631 is ideal in systems where cost?ef fectiveness, reliability, low stand?by power and high power factor are the key parameters: fully stable fccrm and out?of?phase operation. unlike master/slave controllers, the ncp1631 utilizes an interactive?phase approach where the two branches operate independently. hence, the two phases necessarily operate in fccrm, preventing risks of undesired dead?times or continuous conduction mode sequences. in addition, the circuit makes them interact so that they run out?of?phase. the ncp1631 unique interleaving technique substantially maintains the wished 180 phase shift between the 2 branches, in all conditions including start?up, fault or transient sequences. optimized efficiency over the full power range. the ncp1631 optimizes the efficiency of your pfc stage in the whole line/load range. its clamp frequency is a major contributor at nominal load. for medium and light load, the clamp frequency linearly decays as a function of the power to maintain high efficiency levels even in very light load. the power threshold under which frequency reduces is programmed by the resistor placed between pin 6 and ground. to prevent any risk of regulation loss at no load, the circuit further skips cycles when the error amplifier reaches its low clamp level. fast line / load transient compensation. characterized by the low bandwidth of their regulation loop, pfc stages exhibit large over and under?shoots when abrupt load or line transients occur (e.g. at start?up). the ncp1631 dramatically narrows the output voltage range. first, the controller dedicates one pin to set an accurate over?v oltage protection level and interrupts the power delivery as long as the output voltage exceeds this threshold. also, the ncp1631 dynamic response enhancer drastically speeds?up the regulation loop when the output voltage is 4.5% below its desired level. as a matter of fact, a pfc stage provides the downstream converter with a very narrow voltage range. a ?pfcok? signal. the circuit detects when the pfc stage is in steady state or if on the contrary, it is in a start?up or fault condition. in the first case, the ?pfcok? pin (pin15) is in high state and low otherwise. this signal is to disable the downstream converter unless the bulk capacitor is charged and no fault is detected. finally, the downstream converter can be optimally designed for the narrow voltage provided by the pfc stage in normal operation. safety protections. the ncp1631 permanently monitors the input and output voltages, the input current and the die temperature to protect the system from possible over?stresses and make the pfc stage extremely robust and reliable. in addition to the aforementioned ovp protection, one can list: maximum current limit: the circuit permanently senses the total input current and prevents it from exceeding the preset current limit, still maintaining the out?of?phase operation. in?rush detection: the ncp1631 prevents the power switches turn on for the large in?rush currents sequence that occurs during the start?up phase. under?v oltage protection: this feature is mainly to prevent operation in case of a failure in the ovp monitoring network (e.g., bad connection). brown?out detection: the circuit stops operating if the line magnitude is too low to protect the pfc stage from the excessive stress that could damage it in such conditions. thermal shutdown: the circuit stops pulsing when its junction temperature exceeds 150 c typically and resumes operation once it drops below about 100 c (50 c hysteresis). ncp1631 operating modes the ncp1631 drives the two branches of the interleaved in fccrm where each phase operates in critical conduction mode (crm) in the most stressful conditions and in discontinuous conduction mode (dcm) otherwise, acting as a crm controller with a frequency clamp (given by the oscillator). according to the conditions, the pfc stage actually jumps from dcm to crm (and vice versa) with no discontinuity in operation and without degradation of the current shape. the circuit can also transition within an ac line cycle so that: ? crm reduces the current stress around the sinusoid top. ? dcm limits the frequency around the line zero crossing. this capability offers the best of each mode without the drawbacks. the way the circuit modulates the mosfet on?time allows this facility.
ncp1631 www. onsemi.com 10 figure 3. dcm and crm operation within a sinusoid cycle for one branch ncp1631 on?time modulation let?s study the ac line current absorbed by one phase of the interleaved pfc converter. the current waveform of the inductor (l) during one switching period (t sw ) is portrayed by figure 5. the ac line current is the averaged value of the coil current as the result of the emi filter ?polishing? action. hence, the line current produced by one of the phase is: i in 1 2 t 1 l t 1 t 2 t sw v in (eq. 1) where (t sw = t 1 + t 2 + t 3 ) is the switching period and v in is the ac line rectified voltage. equation 1 shows that i in is proportional to v in if t 1 (t 1 t 2 ) t sw is a constant. t 1 (t 1 t 2 ) t sw forcing constant is what the ncp1631 does to perform fccrm operation that is, to operate in discontinuous or critical conduction mode according to the conditions, without degradation of the power factor. figure 4. boost converter figure 5. inductor current in dcm the ncp1631 operates in voltage mode. as portrayed by figure 6, the mosfet on time t 1 is controlled by the signal v ton generated by the regulation block as follows: t 1 c t v ton i t (eq. 2) where: ? c t is the internal timing capacitor ? i t is the internal current source for the timing capacitor. the i t charge current is constant for a given resistor placed on the r t pin. c t is also a constant. hence, the condition t 1 (t 1 t 2 ) t sw to be a constant for proper power factor correction can be changed into: v ton (t 1 t 2 ) t sw is constant. the output of the regulation block (v control ) is linearly changed into a signal (v regul ) varying between 0 and 1.66 v. (v regul ) is the voltage that is injected into the pwm section to modulate the mosfet duty?cycle. however, the ncp1631 inserts some circuitry that processes (v regul ) to form the signal (v ton ) that is used in the pwm section instead of (v regul ) (see figure 7). (v ton ) is modulated in response to the dead?time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current. this modulation leads to: v ton t sw v regul t 1 t 2 (eq. 3 ) v ton t 1 t 2 t sw v regul or: substitution of equation 3 into equation 2 leads to the following on?time expression: t 1 c t t sw v regul t 1 t 2 i t (eq. 4) replacing ?t 1 ? by its expression of equation 4, equation 1 simplifies as follows: i in(phase1) i in(phase2) v in 2l c t v regul i t (eq. 5)
ncp1631 www. onsemi.com 11 given the regulation low bandwidth of the pfc systems, (v control ) and then (v regul ) are slow varying signals. hence, the line current absorbed by each phase is: i in(phase1) i in(phase2) kv in (eq. 6) k constant c t v regul 2li t where: hence, the input current is then proportional to the input voltage and the ac line current is properly shaped. one can note that this analysis is also valid for crm operation that is just a particular case of this functioning where (t 3 =0), which leads to (t 1 +t 2 =t sw ) and (v ton =v regul ). that is why the ncp1631 automatically adapts to the conditions and jumps from dcm and crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. the charging current i t is internally processed to be proportional to the square of the line magnitude. its value is however programmed by the pin 3 resistor to adjust the available on?time as defined by the t on1 to t on4 parameters of the data sheet. from these data, we can deduce: t 1 t on ( s) 50 n r t 2 v pin7 2 (eq. 7) from this equation, we can check that if v pin7 (bo voltage) is 1 v and r t is 20 k (i pin3 = 50 a) that the on?time is 20 s as given by parameter t on1 . since: t on c t v regul i t v regul(max) 1.66 v v pin7 22 v in(rms) k bo where k bo is the scale down factor of the bo sensing network k bo r bo2 r bo1 r bo2 (see brown?out section) we can deduce the total input current value and the average input power: i in(rms) (r t ) 2 v regul 26.9
10 12 lk bo 2 v in,rms (eq. 8) p in,avg (r t ) 2 v regul 26.9
10 12 lk bo 2 (eq. 9) figure 6. pwm circuit and timing diagram figure 7. v ton processing circuit + ? ?> v to n d u ring (t1+t2) ?> 0 v d u rin g t3 (d e a d ?time ) ?> v to n *(t1+t2)/t in average vton + ? timing capacitor s aw ?to o th to pwm latch pwm comparator in 1 s1 s2 c1 r1 skip oa1 of f s3 ov p pfcok in ?ru s h 0.5* (i se nse ? 210 ) oc p the integrator oa1 amplifies the error between v regul and in1 so that in average, (v ton *(t 1 +t 2 )/t sw ) equates v regul . v regul v bocomp (from bo block ) dt (high during dead?time) the ?v ton processing circuit? is ?informed? when there is an ovp condition or a skip sequence, not to over?dimension v ton in that conditions. otherwise, an ovp sequence or a skipped cycle would be viewed as a ?normal? dead?time phase by the circuit and v ton would inappropriately increase to compensate it. (refer to figure 7). the output of the ?v ton processing circuit? is also grounded when the circuit is in off state to discharge the capacitor c1 and initialize it for the next active phase. finally, the ?v ton ? is not allowed to be further increased compared to v regul when the circuit has not completed the start?up phase (pfcok low) and if v bocomp from the brown?out block is high (refer to brown?out section for more information).
ncp1631 www. onsemi.com 12 0,00 50,00 100,00 150,00 200,00 250,00 300,00 350,00 0 2 4 6 8 101214161820 time (ms) vin (v) 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 to n ( s) vin ton figure 8. input voltage and on?time vs. time (example with f sw = 100 khz, pin = 150 w, v ac = 230 v, l = 200 h) regulation block and low output voltage detection a trans?conductance error amplifier with access to the inverting input and output is provided. it features a typical trans?conductance gain of 200 s and a typical capability of 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and monitored by the inverting input (feed?back pin ? pin2). the bias current is minimized (less than 500 na) to allow the use of a high impedance feed?back network. the output of the error amplifier is pinned out for external loop compensation (pin5). typically a type?2 compensator is applied between pin5 and ground, to set the regulation bandwidth below 20 hz, as need in pfc applications (refer to application note and8407). the swing of the error amplifier output is limited within an accurate range: ? it is forced above a voltage drop (v f ) by the ?low clamp? circuitry. when this circuitry is activated, the power demand is minimum and the ncp1631 enters skip mode (the controller stops pulsating) until the clamp is no more active. ? it is clamped not to exceed 3.0 v + the same v f voltage drop. hence, v pin5 features a 3 v voltage swing. v pin5 is then offset down by (v f ) and further divided before it connects to the ?v ton processing block? and the pwm section. finally, the output of the regulation is a signal (?v regul ? of the block diagram) that varies between 0 and 1.66 v. figure 9. regulation block fb v control off + ? e rr o r am p lifier vref + ? 0.955*vref vout low detect 20 a 3v 5r pfcok 230 a vdd ovlflag1 4r skip figure 10. correspondence between v control and v regul v regul (0 .6 v c lamp vo ltage is activated)
ncp1631 www. onsemi.com 13 provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and under?shoots. over?shoots are limited by the over? voltage protection (see ovp section). to contain the under?shoots, an internal comparator monitors the feed?back signal (v pin2 ) and when v pin2 is lower than 95.5% of its nominal value, it connects a 230 a current source to speed?up the charge of the compensation capacitor (c pin5 ). finally, it is like if the comparator multiplied the error amplifier gain by 10. one must note that this circuitry for under?shoots limitation, is not enabled during the start?up sequence of the pfc stage but only once the converter has stabilized (that is when the ? pfcok ? signal of the block diagram, is high). this is because, at the beginning of operation, the pin5 capacitor must charge slowly and gradually for a soft start?up. zero current detection while the on time is constant, the core reset time varies with the instantaneous input voltage. the ncp1631 determines the demagnetization completion by sensing the inductor voltage, more specifically, by detecting when the inductor voltage drops to zero. practically, an auxiliary winding in flyback configuration is taken off of the boost inductor and gives a scaled down version of the inductor voltage that is usable by the controller (figure 12). in that way, the zcd voltage (?v aux ?) falls and starts to ring around zero volts when the inductor current drops to zero. the ncp1631 detects this falling edge and allows the next driver on time. figure 1 shows how it is implemented. for each phase, a comparator detects when the voltage of the zcd winding exceeds 0.5 v. when this is the case, the coil is in demagnetization phase and the latch l zcd is set. this latch is reset when the next driver pulse occurs. l1 d1 cbulk m1 drv1 14 + ? 0.5 v zcd1 16 vcc output buffe r 1 200? s delay vin dt zcd2 1 l2 d2 vout cbulk m2 drv2 11 vcc vin vzcd2 + ? 0.5 v qzcd2 and1 vzcd1 set1 set2 in?rus h in?rus h figure 11. zero current detection rzcd2 rzcd1 negative and positive clamp v dmg1 l zcd qzcd1 q s r q s r q s r s r q q zcd v dmg2 off (from fault management block) clk2 (from phase management block) clk1 (from phase management block) s q r pwm latch ph1 pwm latch ph2 reset signal (from ph2 pwm comparator) reset signal (from ph1 pwm comparator) output buffe r 2 negative and positive clamp to prevent negative voltages on the zcd pins (zcd1 for phase 1 and zcd2 for phase 2), these pins are internally clamped to about 0 v when the voltage applied by the corresponding zcd winding is negative. similarly, the zcd pins are clamped to v zcd(high) (10 v typical), when the zcd voltage rises too high. because of these clamps, a resistor (r zcd of figure 11) is necessary to limit the current from the zcd winding to the zcd pin. the clamps are designed to respectively source and sink 5 ma minimum. it is recommended not to exceed this 5 ma level within the zcd clamps for a proper operation. at startup or after an inactive period (because of a protection that has tripped for instance), there is no energy in the zcd winding and therefore no voltage signal to activate the zcd comparator. this means that the driver will never turn on. to avoid this, an internal watchdog timer is integrated into the controller. if the driver remains low for more than 200 s (typical), the timer sets the l zcd latch as the zcd winding signal would do. obviously, this 200? s delay acts as a minimum off?time if there is no demagnetization winding while it has no action if there is a zcd voltage provided by the auxiliary winding.
ncp1631 www. onsemi.com 14 figure 12. zero current detection timing diagram (v aux is the voltage provided by the zcd winding) current sense the ncp1631 is designed to monitor a negative voltage proportional to total input current, i.e., the current drawn by the two interleaved branches (i in ). as portrayed by figure 13, a current sense resistor (r cs ) is practically inserted within the return path to generate a negative voltage (v cs ) proportional to i in . the circuit uses v cs to detect when i in exceeds its maximum permissible level. to do so, the circuit incorporates an operational amplifier that sources the current necessary to maintain the cs pin voltage null (refer to figure 13). by inserting a resistor r ocp between the cs pin and r cs , we adjust the current that is sourced by the cs pin (i cs ) as follows: [r cs i coil ] [r ocp i cs ] 0 (eq. 10) which leads to: i cs r cs r ocp i coil (eq. 11) in other words, the pin 9 current (i cs ) is proportional to the coil current. a negative clamp protects the circuit from the possible negative voltage that can be applied to the pin. this protection is permanently active (even if the circuit off). the clamp is designed to sustain 5 ma. it is recommended not to sink more than 5 ma from the cs pin for a proper operation. two functions use i cs : the over current protection and the in?rush current detection. over?current protection (ocp) if i cs exceeds i ilim1 (210 a typical), an over?current is detected and the on?time is decreased proportionally to the difference between the sensed current i in and the 210 a ocp threshold. the on?time reduction is done by injecting a current i neg in the negative input of the ?v ton processing circuit? opamp. (see figure 7) i neg 0.5(i cs 210 ) (eq. 12) this current is injected each time the ocp signal is high. the maximum coil current is: i coil(max) r ocp r cs i ilim1 (eq. 13) in?rush current detection when the pfc stage is plugged to the mains, the bulk capacitor is abruptly charged to the line voltage. the charge current (named in?rush current) can be very huge
ncp1631 www. onsemi.com 15 depending on the presence or absence of an effective in?rush limiting circuitry. if the mosfet turns on during this severe transient, it may be over?stressed and finally damaged. that is why , the ncp1631 permanently monitors the input current and delays the mosfet turn on until the in?rush current has vanished. this is the function of the i cs comparison to the i in?rush threshold (14 a typical). when i cs exceeds i in?rush , the comparator output (?in?rush?) is high and prevents the pwm latches from setting (see block diagram). hence, the two drivers cannot turn high and the mosfets cannot switch on. this is to guarantee that the mosfets remain off as long as if the input current exceeds 10% of its maximum value. this feature protects the mosfets from the possible excessive stress it could suffer from if it was allowed to turn on while a huge current flowed through the coil as it can be the case at start?up or during an over?load transient. the propagation delay (i cs < i in?rush ) to (drive outputs high) is in the range of few s. however when the circuit starts to operate, the ncp1631 disables this protection to avoid that the current produced by one phase and sensed by the circuit prevents the other branch from operating. practically, some logic grounds the in?rush protection output when it detects the presence of current cycles with a zero current detection signal provided by the auxiliary winding (figure 13). the cs block performs the over?current protection and the in?rush current detection. 9 ac lin e load cs oc p in?r ush drv 2 negative clamp curr e nt drv 1 drv 1 drv 2 figure 13. current sense block v in i in c in emi filter i cs r cs the pin voltage is maintained to 0 v i cs r ocp i in mirror i cs i cs i cs (i cs is proportional to the coil current) v aux2 v aux1 v out d 2 d 1 l 1 l 2 m 1 m 2 c bulk q zcd1 q zcd2 (from zcd block) i ilim1 = 210 a i in?rush = 14 a over?voltage protection while pfc circuits often use one single pin for both the over?v oltage protection (ovp) and the feed?back, the ncp1631 dedicates one specific pin for the under?voltage and over?voltage protections. the ncp1631 configuration allows the implementation of two separate feed?back networks (see figure 15): 1. one for regulation applied to pin 2. 2. another one for the ovp function (pin 8). figure 14. configuration with one feed?back network for both ovp and regulation fb 1 2 3 4 13 16 14 15 5 6 7 12 10 11 ovp vout (bulk voltage) rout2 rout1 rout3 figure 15. configuration with two separate feed?back networks fb 1 2 3 4 13 16 14 15 5 6 7 12 10 11 ovp vout (bulk voltage) rovp2 rout1 rout2 rovp1 9 8 9 8
ncp1631 www. onsemi.com 16 the double feed?back configuration offers some up?graded safety level as it protects the pfc stage even if there is a failure of one of the two feed?back arrangements. however, if wished, one single feed?back arrangement is possible as portrayed by figure 14. the regulation and ovp blocks having the same reference voltage, the resistance ratio r out2 over r out3 adjusts the ovp threshold. more specifically, the bulk regulation voltage (?v out(nom) ?) is: v out(nom) r out1 r out2 r out3 r out2 r out3
v ref (eq. 14) the ovp level (?v out(ovp) ?) is: v out(ovp) r out1 r out2 r out3 r out2
v ref (eq. 15) the ratio ovp level over regulation level is: v out(ovp) v out(nom) 1 r out3 r out2 (eq. 16) for instance, (v out(nom) = 105% x v out(nom) ) leads to: (r out3 = 5% x r out2 ). when the circuit detects that the output voltage exceeds the ovp level, it maintains the power switch open to stop the power delivery. as mentioned previously, the ?v ton processing circuit? is ?informed? when there is an ovp condition, not to over?dimension v ton in that conditions. otherwise, an ovp sequence would be viewed as a dead?time phase by the circuit and v ton would inappropriately increase to compensate it (refer to figure 7). pfcok / ref5v signal the ncp1631 can communicate with the downstream converter. the signal ?pfcok/ref5v? is high (5 v) when the pfc stage is in normal operation (its output voltage is stabilized at the nominal level) and low otherwise. more specifically, ?pfcok/ref5v? is low: ? during the pfc stage start?up, that is, as long as the output voltage has not yet stabilized at the right level. the start?up phase is detected by the latch ?l stup ? of the block diagram in figure 2. ?l stup ? is set during each ?off? phase so that its output (?stup?) is high when the circuit enters an active phase. the latch is reset when the error amplifier stops charging its output capacitor, that is, when the output voltage of the pfc stage has reached its desired regulation level. at that moment, ?stup? falls down to indicate the end of the start?up phase. ? any time, the circuit is off or a fault condition is detected as described by the ?fault management and off mode? section finally, ?pfcok/ref5v? is high when the pfc output voltage is properly and safely regulated. ?pfcok/ref5v? should be used to allow operation of the downstream converter. oscillator section ? phase management the oscillator generates the clock signal that dictates the maximum switching frequency for the global system ( f osc ). in other words, each of the two interleaved branches cannot operate above the clamp frequency that is half the oscillator frequency ( f osc /2). the oscillator frequency ( f osc ) is adjusted by the capacitor applied to pin 4. typically, a 440 pf capacitor approximately leads to a 120?khz operating frequency, meaning a 60?khz clamp frequency for each branch. the oscillator frequency should be kept below 500 khz (which corresponds to a pin4 capacitor in the range of 100 pf ). as shown by figure 16, two current sources i osc(clamp) (35 a typical) and i osc(ch) (105 a typical) charge the pin 4 capacitor until its voltage exceeds v osc(high) (5 v typically). at that moment, the output of the comp_osc comparator (?sync? of figure 16) turns high and changes the comp_osc reference threshold that drops from v osc(high) down to v osc(low) (hysteresis). the system enters a discharge phase where the i ch current source is disabled and instead a sink current i osc(disch) (105 a typ.) discharges the pin 4 capacitor. this sequence lasts until v pin4 goes below v osc(low) when the ?sync? signal turns low and a new charging phase starts. a divider by two uses the ?sync? information to manage the phases of the interleaved pfc: the first sync pulse sets ?phase 1?, the second one, ?phase 2?, the third one phase 1 again... etc... according to the selected phase, the ?sync? signal sets the relevant ?clock generator latch? that will generate the clock signal (?clk1? for phase 1, ?clk2? for phase 2) when sync drops to zero (falling edge detector). so, the drivers are synchronized to sync falling edge. actually, the drivers cannot turn on at this very moment if the demagnetization of the coil is not yet complete (crm operation). in this case, the clock signal is maintained high until the driver turns high (the clock generator latches are reset by the corresponding driver is high ? reset on rising edge detector). also, the discharge time can be prolonged if when v pin4 drops below v osc(low) , the driver of the phase cannot turn on because the core is not reset yet (crm operation). in this case, v pin4 decreases until the driver turns high. the further discharge of v pin4 below v osc(low) helps maintain a substantial 180 phase shift in crm that is in essence, guaranteed in dcm. in the two conditions (crm or dcm), operation is stable and robust. figure 17 portrays the clock signal waveforms in different cases: ? in fixed frequency operation (dcm), the cycle time of the coil current is shorter than an oscillator period. hence, as soon as the clock signal goes high, the driver can turn on and reset the clock generator latch. the clock signal is then a short pulse.
ncp1631 www. onsemi.com 17 ? however, the coil current can possibly be non zero when the clock signal turns high. the circuit would enter continuous conduction mode (ccm) if the mosfet turned on in that moment. in order to avoid ccm operation, the clock is prevented from setting the pwm latch until the core is reset (that is as low as ?v zcd ? of figure 8 is low). the clock signal remains high during this waiting phase (refer to figure 12). hence the next mosfet conduction time occurs as soon as the coil current has totally vanished. in other words, critical conduction mode (crm) operation is obtained. the clamp frequency can be computed using the following equation: f osc 60 c osc 10 p (eq. 17) where c osc is the pin 4 external capacitor and c pin the pin 4 parasitic capacitance (about 10 pf). os c clk1 ge nera tion latch s q r cl k1 drv 1 co mp _osc current clk2 ge nera tion latch s q r cl k2 drv 2 divider by tw o p h ase1 p hase2 sync syncbar syncbar q_ph1 q_ph2 q_ph2 q_ph1 syncbar pfcok ffold figure 16. oscillator block r ff i ff v regul i ff mirror 105 a v regul circuitry for frequency foldback c osc i osc(disch) = i ff i osc(ch) = i ff i osc(clamp) v osc(high) / v osc(low)
ncp1631 www. onsemi.com 18 figure 17. typical waveforms (t delay not shown here for the sake of simplicity) frequency foldback in addition, the circuit features the frequency fold?back function to improve the light load efficiency. practically, the oscillator charge and discharge currents (i osc(ch) and i osc(disch) of figure 16) are not constant but dependent on the power level. more specifically, i osc(ch) and i osc(disch) linearly vary as a function of v control output of the regulation block that thanks to the feed?forward featured by the ncp1631, is representative of the load. the practical implementation is portrayed by figure 16. ?v regul ? is the signal derived from v control that is effectively used to modulate the mosfet on?time. v regul is buffered and applied to pin 6 (?frequency fold?back? pin). a resistor r ff is to be connected to pin 6 to sink a current proportional to v regul i pin6 i ff v regul r ff . this current is clamped not to exceed 105 a and copied by a current mirror to form i osc(ch) and i osc(disch) . as a matter of fact, the oscillator charge current is: i osc(ch) i osc(clamp) v regul r ff (eq. 18) if v regul r ff 105 a i osc(ch) i osc(clamp) i osc(ch1) i osc(cht1) 140 a otherwise the oscillator charge current is then an increasing function of v regul and is clamped to 140 a. the oscillator discharge current is: i osc(disch) v regul r ff (eq. 19) if v regul r ff 105 a i osc(disch) i osc(disch1) 105 a otherwise the oscillator discharge current is also an increasing function of v regul and is clamped to105 a. as a consequence, the clamp frequency is also an increasing function of v regul until it reaches a maximum value for (i ff = 105 a). if we consider the clamp frequency f osc computed by equation 17 as the nominal value obtained at full load and if we name it ?f osc(nom) ?:
ncp1631 www. onsemi.com 19 f osc f osc(nom) (eq. 20) if v regul r ff
105 a f osc v regul (r ff i osc(clamp) v regul ) 60 r ff (r ff i osc(clamp) 2v regul )
f osc(nom) if v regul r ff
105 a let?s illustrate this operation on an example. v regul is the control signal that varies between 0 and 1.66 v, (v regul = 1.66 v) corresponding to the maximum power (p in ) hl that can virtually be delivered by the pfc stage as selected by the timing resistor (for more details, you can refer to the application note and8407). if one decides to start to reduce the clamp frequency when the power goes below (p in ) hl /2, the oscillator charge current should start to decrease when v regul is 0.83 v. hence, the pin 6 resistor (?r ff ?) must be selected so that pin 6 sources 105 a when v regul equates 0.83 v: r ff 0.83 v 105 a 7.9 k (eq. 21) let?s take (r ff = 8.2 k ) which is a normalized value. this selection leads to: f osc f osc(nom) (eq. 22) if v regul 8.2 k
105 860 mv f osc v regul (r ff i osc(clamp) v regul ) 492 m(r ff i osc(clamp) 2v regul )
f osc(nom) if v regul 860 mv for instance, if the nominal frequency (f osc(nom) ) is 120 khz, the following characteristic is obtained. figure 18. fold?back characteristic of the clamp frequency with r ff = 8.2 k and f osc(nom) = 120 khz 0 0.5 1 1.5 0 50 100 150 v regul (v) f osc (khz) f osc(nom) = 120 khz if pin6 is grounded (accidently or not), the circuit operates properly with a constant 140 a oscillator charge current and a 105 a discharge current. the clamp frequency equates its nominal value over the whole load range. if pin6 is open, the oscillator charge current is equal to i osc(clamp) but the oscillator discharge current is null and hence the pfc stage cannot operate. a minimum discharge current and hence a minimum clamp frequency can be forced by placing a resistor between pin 4 and ground. for instance, a 1.5?m resistor forces a 3.3? a discharge current when the oscillator capacitor is fully charged and about 2.6 a when it is near the oscillator low threshold (4 v). a transistor pulls the pin 6 down during startup to disable the frequency fold?back function. skip mode the circuit features the frequency fold?back that leads to a very efficient stand?by mode. in order to ensure a proper regulation in no load conditions even if this feature is not used (pin 6 grounded), the circuit skips cycles when the error amplifier output is at its minimum level. the error amplifier output is maintained between about 0.6 v and 3.6 v thanks to active clamps. a skip sequence occurs as long as the 0.6 v clamp circuitry is triggered and switching operation is recovered when the clamp is inactive.
ncp1631 www. onsemi.com 20 brown?out protection the brown?out pin receives a portion of the input voltage (v in ). as v in is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of (v in ) is applied to the brown?out pin. figure 19. brown?out block bo em i filter ac line ci r c uitr y fo r brown?out detection reset res et bo_nok 1 v 7 a vdd 980 mv clamp current m irror rt irt_ low this pnp transistor maintains the bo pin below the bo threshold when the circuit is not fed state of the bo block enough to control the r cs c bo c in v in r rt r bo1 r bo2 v bo v bo feed?forward circuitry i rt i rt i rt < 7 a s 1 s 2 v bocomp t delay 50-ms delay 50-ms delay s r q l bo this voltage (?v bocomp ?) is high when v pin7 is below 1 v the main function of the bo block is to detect too low input voltage conditions. a 7? a current source lowers the bo pin voltage when a brown?out condition is detected. this is for hysteresis purpose as required by this function. in nominal operation, the voltage applied to pin7 must be higher than the 1 v internal voltage reference. in this case, the output of the comparator bo_comp (v bocomp ) is low (see figure 19). conversely, if v pin7 goes below 1 v, the bo_comp output t urns high and a 965 mv voltage source is connected to the bo pin to maintain the pin level near 1 v. then, a 50?ms blanking delay is activated during which no fault is detected. the main goal of the 50?ms lag is to help meet the hold?up requirements. in case of a short mains interruption, no fault is detected and hence, the ?pfcok? signal remains high and does not disable the downstream converter. in addition, pin7 being kept at 965 mv, there is almost no extra delay between the line recovery and the occurrence of a proper voltage applied to pin2, that otherwise would exist because of the large capacitor typically placed between pin7 and ground to filter the input voltage ripple. as a result, the ncp1631 effectively ?blanks? any mains interruption that is shorter than 25 ms (minimum guaranteed value of the 50?ms timer). at the end of this 50?ms blanking delay, another timer is activated that sets a 50?ms window during which a fault can be detected. this is the role of the second 50?ms timer of figure 19: ? if the output of opamp is high at the end of the first delay (50?ms blanking time) and before the second 50?ms delay time is elapsed, a brownout condition is detected ? if the output of opamp remains low for the duration of the second delay, no fault is detected. when the ?bo_nok? signal is high: ? the drivers are disabled, the ?v control ? pin is grounded to recover operation with a soft?start when the fault has gone and the ?pfcok? voltage turns low to disable the downstream converter. ? the opamp output is separated from pin7 (figure 19) to prevent the operational amplifier from maintaining 1 v on pin7 (as done by the switches s 1 and s 2 in the representation of figure 19). instead, v pin2 drops to the value that is externally forced (by v in , r bo1 , r bo2 and c bo2 in figure 19). as a consequence, the opamp output remains high and the ?bo_nok? signal stays high until the line recovers.
ncp1631 www. onsemi.com 21 ? the 7? a current source is enabled that lowers the pin7 voltage for hysteresis purpose. a short delay (t delay ) is added to get sure that these three actions are properly done before the pfc driver is disabled and the ?v control ? and ?pfcok? pins are grounded. at startup (and in uvlo situations that is when the vcc voltage is not sufficient for operation), a pnp transistor ensures that the bo pin voltage remains below the 1 v threshold until v cc reaches v cc(on) . this is to guarantee that the circuit starts operation in the right state, that is, ?bonok? high. when v cc exceeds v cc(on) , the pnp transistor turns off and the circuit enables the 7? a current source (i bo ). also, (i bo ) is enabled whenever the part is in off?mode, but at startup, i bo is disabled until v cc reaches v cc(on) . brown?out resistors calculation the bo resistors can be calculated with the following equations (for more details, refer to the application note and8407) r bo1 (v in,avg ) boh (v in,avg ) bol 1 f line 10 3 f line i hyst (eq. 23) r bo2 r bo1 (v in,avg ) bol v bo(th) 1 f bo 3 f line 1 (eq. 24) feed?forward as shown by figure 19, the bo circuit also generates an internal current proportional to the input voltage average value (i rt ). the pin7 voltage is buffered and made available on pin 3. placing a resistor between pin 3 and ground, enables to adjust a current proportional to the average input voltage. this current (i rt ) is internally copied and squared to form the charge current for the timing capacitor of each phase. since this current is proportional to the square of the line magnitude, the conduction time is made inversely proportional to the line magnitude. this feed?forward feature makes the transfer function and the power delivery independent of the ac line level. only the regulation output (v regul ) controls the power amount. if the i rt current is too low ( below 7 a), the controller goes in off mode to avoid damaging the mosfets with too long conduction time. thermal shutdown (tsd) an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140 c typically. the output stage is then enabled once the temperature drops below about 80 c (60 c hysteresis). the temperature shutdown keeps active as long as the circuit is not reset, that is, as long as v cc keeps higher than v cc reset. the reset action forces the tsd threshold to be the upper one (140 c). this ensures that any cold start?up will be done with the right tsd level. under?voltage lockout section the ncp1631 incorporates an under?voltage lockout block to prevent the circuit from operating when the power supply is not high enough to ensure a proper operation. an uvlo comparator monitors the pin 12 voltage (v cc ) to allow the ncp1631 operation when v cc exceeds 12 v typically. the comparator incorporates some hysteresis (2.0 v typically) to prevent erratic operation as the v cc crosses the threshold. when v cc goes below the uvlo comparator lower threshold, the circuit turns off. the circuit off state consumption is very low: < 50 a. this low consumption enables to use resistors to charge the v cc capacitor during the start?up without the penalty of a too high dissipation. output drive section the circuit embeds two drivers to control the two interleaved branches. each output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. the gate drive is kept in a sinking mode whenever the under?voltage lockout (uvlo) is active or more generally whenever the circuit is off. its high current capability (?500 ma/+800 ma) allows it to effectively drive high gate charge power mosfet. reference section the circuit features an accurate internal reference voltage (v ref ). v ref is optimized to be 2.4% accurate over the temperature range (the typical value is 2.5 v). v ref is the voltage reference used for the regulation and the over?voltage protection. the circuit also incorporates a precise current reference (i ref ) that allows the over?current limitation to feature a 6% accuracy over the temperature range. fault management and off mode the circuit detects a fault if the r t pin is open (figure 20). practically, if the pin sources less than 7 a, the ?i rt_low ? signal sets a latch that turns off the circuit if its output (r t(open) ) is high. a 30? s blanking time avoids parasitic fault detections. the latch is reset when the circuit is in uvlo state (too low v cc levels for proper operation).
ncp1631 www. onsemi.com 22 vdd regul vcc internal thermal shutdown tsd of f uvlo stdwn iref vcc_ok vref fault management uvp 12 v / 10 v bo_nok r s q rt(open) figure 20. fault management block irt_low (ipin3 < 7 a) 30? s blanking time when any of the following faults is detected: ? brown?out (?bo_nok?) ? under?v oltage protection (?uvp?) ? latch?off condition (?stdwn?) ? die over?temperature (?tsd?) ? too low current sourced by the r t pin (?r t(open) ?) ? ?uvlo? (improper vcc level for operation) the circuit turns off. in this mode, the controller stops operating. the major part of the circuit sleeps and its consumption is minimized (< 500 a). more specifically, when the circuit is in off state: ? the two drive outputs are kept low ? the 7? a current source of the brown?out block is enabled to set the proper start?up bo threshold if vcc is high enough for proper operation. if not, the brown-out pin is pulled down by a pnp transistor for a proper input voltage sensing when the circuit recovers operation (see brown-out section). ? the pin5 capacitor (v control ) is discharged and kept grounded along the off time, to initialize it for the next operating sequence, where it must be slowly and gradually charged to offer some soft?start. ? the ?pfcok? pin is grounded. ? the output of the ?v ton processing block? is grounded when the circuit recovers after a fault, the first watchdog time is around 20 s instead of 200 s to allow a faster re?start. in off mode at startup, the consumption is very low (< 50 a). the brown?out block is initialized not to allow operation (?bo_nok? high) by default. the pnp clamp is active and maintains the bo pin level below 1 v. the 7? a current source is enabled only when v cc reaches v cc(on) threshold.
ncp1631 www. onsemi.com 23 figure 21. start?up and brown out conditions
ncp1631 www. onsemi.com 24 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent? marking.pdf. s cillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data she ets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for e ach customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designe d, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such u nintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this l iterature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1631/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative

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